unisonic technologies co., ltd 82XX preliminary linear integrated circuit www.unisonic.com.tw 1 of 8 copyright ? 2010 unisonic technologies co., ltd qw-r502-326.c monolithic ic 82XX series ? description the normal operation of the utc 82XX is that while the power is turned on or interrupted, detect power supply voltage and then reset the system accurately. the internal circuits of the utc 82XX include a built-in fixed delay time generating circuit. with a counter timer using an analog/digital hybrid circuit, the utc 82XX as new low reset type system reset ics expands the delay time series. these ics can be used in a vari ety of cpu systems and other logic systems. ? features * internal fixed delay time setting by counter timer * grate delay time temperatur e characteristics:800ppm/c * operating limit voltage as 0.65v(typ.) * hysteresis voltage provided: 50mv(typ.) * circuit current while on i ccl =300a(typ.) * circuit current while off i cch =200a(typ.) * halogen free ? ordering information ordering number package packing 82XXg-x-af5-r sot-25 tape reel notes: xx: output voltage, refer to marki ng information. x : delay time, refer to electrical characteristics of "h" transport delay time
82XX preliminary linear integrated circuit unisonic technologies co., ltd 2 of 8 www.unisonic.com.tw qw-r502-326.c ? marking information package voltage code marking sot-25 25:2.5v 27:2.7v 2k:2.93v 321 xx x x 5 4 voltage code l: lead free g: halogen free month x ? pin configuration 3 2 1 4 5 reset nc v out gnd v cc ? pin description pin no. pin name description 1 v out output pin 2 nc connected nothing 3 reset reset control pin 4 v cc supply voltage 5 gnd ground
82XX preliminary linear integrated circuit unisonic technologies co., ltd 3 of 8 www.unisonic.com.tw qw-r502-326.c ? block diagram 47k 47k
82XX preliminary linear integrated circuit unisonic technologies co., ltd 4 of 8 www.unisonic.com.tw qw-r502-326.c ? absolute maximum rating (ta=25c) parameter symbol ratings unit power supply voltage v cc -0.3~+10 v manual reset input voltage v reset -0.3~+10 v power dissipation p d 400 mw operating temperature t opr -20~+75 c storage temperature t stg -40~+125 c note: absolute maximum ratings are those values beyo nd which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? electrical characteristics (ta=25c, unless otherwise specified) v s =2.5v~2.93v parameter symbol test conditions min typ max unit detection voltage v s v ol 0.4v, v cc =h l, r l =470 ? (see test circuit 1) v s -0.15v v s v s +0.15v v low-level output voltage v ol v cc =v s(min) -0.05v, r l =470 ? (see test circuit 1) 0.1 0.4 v operating power supply voltage v opl r l =4.7k ? , v ol 0.4v 0.65 0.85 v hysteresis voltage v s v cc =l h l , r l =470 ? (see test circuit 1) 30 50 100 mv detection voltage temperature coefficient t s v r l =470 ? , ta=-20 c ~+75 c (see test circuit 1) 0.01 %/ c output leakage current i oh v cc =10v (see test circuit 1) 0.1 a on i ccl v cc = v s(min) -0.05v, r l = (see test circuit 1) 300 600 a circuit current off i cch v cc =v s(typ) /0.85v, r l = (see test circuit 1) 200 350 a p 30 50 75 ms q 60 100 150 ms r 120 200 300 ms s 240 400 600 ms "h" transport delay time t plh r l =4.7k ? , c l =100pf (note 1) (see test circuit 2) t 480 800 1200 ms "l" transport delay time t phl r l =4.7k ? , c l =100pf (note 1) (see test circuit 2) 10 s output current while on 1 i ol1 v cc =vs min.-0.05v, r l =0 ? (see test circuit 1) 8 ma output current while on 2 i ol2 ta=-20 c ~+75 c , r l =0 ? (note 2) (see test circuit 1) 6 ma input high voltage v resh 2.0 v input high current i resh v reset =2v 80 a manual reset pin input low voltage v resl 0.8 v notes: 1. t plh : v cc = (v s(typ) -0.4v) ? (v s(typ) +0.4v) t phl : v cc = (v s(typ) +0.4v) ? (v s(typ) -0.4v) 2. v cc =v s(min) -0.15v 3. v out pin is low when manual reset pin is high. v out pin is high when manual reset pin is low.
82XX preliminary linear integrated circuit unisonic technologies co., ltd 5 of 8 www.unisonic.com.tw qw-r502-326.c ? test circuits a1 a2 v1 10f/10v r l v cc v out gnd manual reset v cc v2 test circuit 1 a: dc ammeter v: dc voltmeter crt: oscilloscope r l =4.7k (2)input pulse input pulse c l= 100pf 10f/10v 5.0v 0v v s 0.8v 4.9 4.1 note input model is an example for 82XX 0.2f/10v v out gnd manual reset v cc crt test circuit 2
82XX preliminary linear integrated circuit unisonic technologies co., ltd 6 of 8 www.unisonic.com.tw qw-r502-326.c ? timing chart v cc/ v out (v)
82XX preliminary linear integrated circuit unisonic technologies co., ltd 7 of 8 www.unisonic.com.tw qw-r502-326.c ? typical application circuits to v cc 1. normal hard reset note: connect a capacitor between ic v cc and gnd pins if v cc line impedance is high. r l to cpu reset pin v out gnd manual reset v cc to v cc r l to cpu reset pin manual sw 2. manual reset v out pin low for manual switch on. v out pin high for manual switch off. note: connect a capacitor between ic v cc and gnd pins if v cc line impedance is high. v out gnd manual reset v cc to v cc 3. mute circuit r l to mute circuit note: connect a capacitor between ic v cc and gnd pins if v cc line impedance is high. v out gnd manual reset v cc
82XX preliminary linear integrated circuit unisonic technologies co., ltd 8 of 8 www.unisonic.com.tw qw-r502-326.c utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
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